The transmission of a serial digital data stream from a transmitter to a receiver requires the synchronization of the receiver with clock pulse information that is comprised in the transmitted data stream, such synchronization being required in order to be able to reproduce the transmitted data. For this purpose phase contrailer devices are used that, in English, are also called phaselocked loops (PLL).
From EP 0 556 984 B1 a phase-locked loop for synchronizing a serial data bit stream is known in which an input signal and a bit clock pulse signal that is generated by a voltage-controlled oscillator are fed to a phase comparator. The phase comparator generates, as a function of the phase difference of the signals present at the inputs of the phase comparator, an error signal that, depending on the result of the comparison, causes a low-pass filter connected in outgoing circuit to increase or decrease a control voltage present at a voltage-controlled oscillator.
A disadvantage of this known control device is the fact that such a phase controller device is relatively inflexible due to its embodiment in hardware.
If an external microcontroller is coupled to a clock pulse generator, as is known from EP 0 556 984 B1, then the synchronization is done by software stored and executed therein via interrupts or polling (cyclic query). This requires a complicated software design since It must make it possible to be able to handle interrupts of this type in a timely manner.
Such a method is known from EP 0 840 458 B1. Therein the external microcontroller is outside of the phase-locked loop and gives the division ratio, corresponding to a manual input signal, to a programmable frequency divider. The frequency divider divides the signal of a voltage-controlled oscillator. The output clock pulse signal of the frequency divider is fed to an input of a phase detector. At the other input of the phase detector a reference clock pulse signal with a fixed reference frequency is present.
Furthermore, it Is a known practice to embody a phase controller device as a so-called software PLL, which is realized by a program executed by a microcontroller. The microcontroller compares the temporal occurrence of the synchronous clock pulse signal present at one input to an expected temporal occurrence and changes variable values in such a manner that the expected temporal occurrence agrees with the actual synchronous clock pulse signal. A disadvantage of such a form of realization of a PLL is the fact that the controller, due to the time needed for the execution of the program stored in it, must operate at a particularly high clock pulse frequency. This makes particularly great demands on the performance of the microcontroller, which thus requires more energy for its operation and is more time-consuming and more expensive to acquire. Furthermore, in phase controller devices of this type an unforeseeable phase error, on the order of magnitude of at most the time required for processor to execute a single command, appears as a source of jitter, which leads to additional phase noise.
Finally, It is a practice known from U.S. Pat. No. 5,387,913 to implement, in a single integrated circuit, a phase controller device together with a digital signal processor that provides a manual input signal to specify a tuning frequency of a radio receiver.
The present invention is based on the technical problem of specifying a phase controller device that is also suitable for input signals with clock pulse frequencies that are high relative to the processing speed of the microcontroller used and that mitigates or eliminates the described disadvantages of the state of the art.